From 8c49ec6d86599df54212f0abc7b7281e8b89f11c Mon Sep 17 00:00:00 2001
From: Pablo Rodriguez <prodriguez@noreply.git.rodlop.net>
Date: Fri, 29 Nov 2024 19:32:43 -0500
Subject: [PATCH] fixed arithmetic and logic (8XXX) instructions

interpreter now passes Timendus' flags test
---
 Interpreter.cpp | 29 ++++++++++++++++-------------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/Interpreter.cpp b/Interpreter.cpp
index d1dbcba..bea55aa 100644
--- a/Interpreter.cpp
+++ b/Interpreter.cpp
@@ -212,27 +212,30 @@ void Interpreter::executeArithmetic(Opcode opcode, int iReg, reg_t operand) {
   case Opcode::XOR:  mvReg[iReg] ^= operand; break;
   case Opcode::RAND: mvReg[iReg]  = rand() & operand; break;
   case Opcode::LSH:
-    mvReg[R_VF] = (mvReg[iReg] & 0x80) ? 1 : 0;
-    mvReg[iReg] <<= 1;
+    mvReg[iReg] = operand << 1;
+    // VF = shifted out bit
+    mvReg[R_VF] = (operand & 0x80) ? 1 : 0;
     break;
   case Opcode::RSH:
-    mvReg[R_VF] = (mvReg[iReg] & 0x01) ? 1 : 0;
-    mvReg[iReg] >>= 1;
+    mvReg[iReg] = operand >> 1;
+    // VF = shifted out bit
+    mvReg[R_VF] = (operand & 0x01) ? 1 : 0;
     break;
   case Opcode::ADD:
-    tmp = mvReg[iReg] + operand;
-    mvReg[R_VF] = (tmp < mvReg[iReg]) ? 1 : 0;
-    mvReg[iReg] = tmp;
+    mvReg[iReg] = mvReg[iReg] + operand;
+    // VF = 1 if carry occurs, VF = 0 if no carry
+    mvReg[R_VF] = (mvReg[iReg] < operand) ? 1 : 0;
     break;
   case Opcode::SUB:
-    tmp = mvReg[iReg] - operand;
-    mvReg[R_VF] = (tmp > mvReg[iReg]) ? 1 : 0;
-    mvReg[iReg] = tmp;
+    tmp = mvReg[iReg];
+    mvReg[iReg] = mvReg[iReg] - operand;
+    // VF = 0 if borrow occurs, VF = 1 if no borrow
+    mvReg[R_VF] = (mvReg[iReg] > tmp) ? 0 : 1;
     break;
   case Opcode::SUB2:
-    tmp = operand - mvReg[iReg];
-    mvReg[R_VF] = (tmp > operand) ? 1 : 0;
-    mvReg[iReg] = tmp;
+    mvReg[iReg] = operand - mvReg[iReg];
+    // VF = 0 if borrow occurs, VF = 1 if no borrow
+    mvReg[R_VF] = (mvReg[iReg] > operand) ? 0 : 1;
     break;
   case Opcode::JEQ:
     if(mvReg[iReg] == operand) {