module register #(
	parameter WIDTH = 32,
	parameter RESET = 0
) (
	input  logic             clock,
	input  logic             reset,
	input  logic             write_en,
	input  logic [WIDTH-1:0] next,
	output logic [WIDTH-1:0] value
);

	always_ff @(posedge clock, posedge reset)
		if(reset)
			value <= RESET;
		else if(write_en)
			value <= next;

endmodule