module Clock_divider #(
    parameter CLOCK_RATIO = 100_000_000
) (
    input      clock_in,
    output reg clock_out
);
    
    reg [$clog2(CLOCK_RATIO)-1:0] counter;
    
    initial begin
        clock_out = 1'b0;
        counter = 0;
    end
    
    always @(posedge clock_in) begin
        clock_out <= (counter >= CLOCK_RATIO-1);
        counter <= (counter >= CLOCK_RATIO-1 ? 0 : counter + 1);
    end

endmodule