set  PROJECT_DIR ..
set  OUTPUT_DIR  ./output
set  PART_NO     xc7a35tcpg236-1

file mkdir $OUTPUT_DIR

read_verilog [ glob $PROJECT_DIR/rtl/*.v ]
read_xdc     $PROJECT_DIR/vivado_flow/Basys3_Master.xdc

synth_design          -top Basys3_Top -rtl -include_dirs $PROJECT_DIR/rtl
start_gui