module Seven_segment_bcd(
    input            clock,
    input     [13:0] value,
    input      [1:0] sel,
    output reg [6:0] seg
);

    wire [17:0] bcd;
    wire [3:0]  bcd_digit;
    
    initial begin
        seg = 0;
    end

    Bin2bcd #(.W(14)) bin2bcd (
        .bin(value),
        .bcd(bcd)
    );
    
    assign bcd_digit = bcd[4*sel +: 4];
    
    always @(posedge clock) begin
        case(bcd_digit)
                     // GFEDCBA
        4'd0: seg <= 7'b1000000;
        4'd1: seg <= 7'b1111001;
        4'd2: seg <= 7'b0100100;
        4'd3: seg <= 7'b0110000;
        4'd4: seg <= 7'b0011001;
        4'd5: seg <= 7'b0010010;
        4'd6: seg <= 7'b0000010;
        4'd7: seg <= 7'b1011000;
        4'd8: seg <= 7'b0000000;
        4'd9: seg <= 7'b0010000;
        default: seg <= 7'bx;
        endcase
    end

endmodule