module Seven_segment_timing (
    input            clock,
    input            clock_en,
    output reg [1:0] sel,
    output reg [3:0] an
);

    initial begin
        sel = 0;
        an = 0;
    end
    
    always @(posedge clock) begin
        an <= ~(4'b0001 << sel);
        if(clock_en)
            sel <= sel + 1;
    end

endmodule