`timescale 100ps/10ps

module testbench ();

    reg clk;
    initial clk = 1'b0;
    always #5 clk = ~clk;
    
    wire slow_clk;
    wire [1:0] segment_select;
    reg  [13:0] counter;
    
    Clock_divider #(.CLOCK_RATIO(4)) clock_divider (
        .clock_in(clk),
        .clock_out(slow_clk)
    );
    
    Blinky uut (
        .clock(clk),
        .clock_en(slow_clk)
    );
    
    Seven_segment_timing seven_segment_timing (
        .clock(clk),
        .sel(segment_select)
    );
    
    Seven_segment_bcd seven_segment_bcd (
        .clock(clk),
        .value(counter),
        .sel(segment_select)
    );
    
    VGA_timing vga (
        .clock(clk),
        .clock_en(1'b1)
    );
    
    always @(posedge clk) begin
        if(slow_clk) counter <= counter + 1;
    end
    
    initial begin
        $display("Hello, World!");
        $display("Simulation started.");
        
        $dumpfile("output/testbench.vcd");
        $dumpvars(0, testbench);
        $display("Writing to output/testbench.vcd");
        
        #5000 $finish();
    end

endmodule