set  PROJECT_DIR ..
set  OUTPUT_DIR  ./output
set  PART_NO     xc7a35tcpg236-1

file mkdir $OUTPUT_DIR

read_verilog [ glob $PROJECT_DIR/rtl/*.v ]
read_xdc     $PROJECT_DIR/vivado_flow/Basys3_Master.xdc

synth_design          -top Basys3_Top -part $PART_NO -include_dirs $PROJECT_DIR/rtl
write_checkpoint      -force $OUTPUT_DIR/post_synth.dcp
report_timing_summary -file $OUTPUT_DIR/post_synth_timing_summary.rpt
report_power          -file $OUTPUT_DIR/post_synth_power.rpt

opt_design
place_design
phys_opt_design
write_checkpoint      -force $OUTPUT_DIR/post_place.dcp
report_timing_summary -file $OUTPUT_DIR/post_place_timing_summary.rpt

route_design
write_checkpoint         -force $OUTPUT_DIR/post_route.dcp
report_timing            -sort_by group -max_paths 100 -path_type summary -file $OUTPUT_DIR/post_route_timing.rpt
report_timing_summary    -file $OUTPUT_DIR/post_route_timing_summary.rpt
report_clock_utilization -file $OUTPUT_DIR/clock_util.rpt
report_utilization       -file $OUTPUT_DIR/post_route_util.rpt
report_power             -file $OUTPUT_DIR/post_route_power.rpt
report_drc               -file $OUTPUT_DIR/post_imp_drc.rpt

write_bitstream -force $OUTPUT_DIR/$PART_NO.bit