fixed arithmetic and logic (8XXX) instructions

interpreter now passes Timendus' flags test
This commit is contained in:
2024-11-29 19:32:43 -05:00
parent 830ab9eda7
commit 8c49ec6d86

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@@ -212,27 +212,30 @@ void Interpreter::executeArithmetic(Opcode opcode, int iReg, reg_t operand) {
case Opcode::XOR: mvReg[iReg] ^= operand; break; case Opcode::XOR: mvReg[iReg] ^= operand; break;
case Opcode::RAND: mvReg[iReg] = rand() & operand; break; case Opcode::RAND: mvReg[iReg] = rand() & operand; break;
case Opcode::LSH: case Opcode::LSH:
mvReg[R_VF] = (mvReg[iReg] & 0x80) ? 1 : 0; mvReg[iReg] = operand << 1;
mvReg[iReg] <<= 1; // VF = shifted out bit
mvReg[R_VF] = (operand & 0x80) ? 1 : 0;
break; break;
case Opcode::RSH: case Opcode::RSH:
mvReg[R_VF] = (mvReg[iReg] & 0x01) ? 1 : 0; mvReg[iReg] = operand >> 1;
mvReg[iReg] >>= 1; // VF = shifted out bit
mvReg[R_VF] = (operand & 0x01) ? 1 : 0;
break; break;
case Opcode::ADD: case Opcode::ADD:
tmp = mvReg[iReg] + operand; mvReg[iReg] = mvReg[iReg] + operand;
mvReg[R_VF] = (tmp < mvReg[iReg]) ? 1 : 0; // VF = 1 if carry occurs, VF = 0 if no carry
mvReg[iReg] = tmp; mvReg[R_VF] = (mvReg[iReg] < operand) ? 1 : 0;
break; break;
case Opcode::SUB: case Opcode::SUB:
tmp = mvReg[iReg] - operand; tmp = mvReg[iReg];
mvReg[R_VF] = (tmp > mvReg[iReg]) ? 1 : 0; mvReg[iReg] = mvReg[iReg] - operand;
mvReg[iReg] = tmp; // VF = 0 if borrow occurs, VF = 1 if no borrow
mvReg[R_VF] = (mvReg[iReg] > tmp) ? 0 : 1;
break; break;
case Opcode::SUB2: case Opcode::SUB2:
tmp = operand - mvReg[iReg]; mvReg[iReg] = operand - mvReg[iReg];
mvReg[R_VF] = (tmp > operand) ? 1 : 0; // VF = 0 if borrow occurs, VF = 1 if no borrow
mvReg[iReg] = tmp; mvReg[R_VF] = (mvReg[iReg] > operand) ? 0 : 1;
break; break;
case Opcode::JEQ: case Opcode::JEQ:
if(mvReg[iReg] == operand) { if(mvReg[iReg] == operand) {