Files
fpga_baseball_scoreboard/rtl/baseball_controlpath.sv
2025-04-06 00:11:28 -04:00

74 lines
1.6 KiB
Systemverilog

`include "constants.sv"
module baseball_controlpath (
input logic got_strike,
input logic got_ball,
input logic got_foul,
input logic got_hit,
input logic got_out,
input logic strikeout,
input logic walk,
input logic three_outs,
input logic game_ended,
input logic [1:0] strike_count,
input logic team_active,
output logic [1:0] strike_mut_sel,
output logic [1:0] ball_mut_sel,
output logic [1:0] out_mut_sel,
output logic inning_mut_sel,
output logic team_toggle
);
always_comb begin
strike_mut_sel = `STRIKE_NOCHANGE;
ball_mut_sel = `BALL_NOCHANGE;
out_mut_sel = `OUT_NOCHANGE;
inning_mut_sel = `INNING_NOCHANGE;
team_toggle = 1'b0;
if(!game_ended) begin
if(strikeout) begin
strike_mut_sel = `STRIKE_ZERO;
ball_mut_sel = `BALL_ZERO;
out_mut_sel = `OUT_PLUSONE;
end
if(walk) begin
strike_mut_sel = `STRIKE_ZERO;
ball_mut_sel = `BALL_ZERO;
end
if(three_outs) begin
strike_mut_sel = `STRIKE_ZERO;
ball_mut_sel = `BALL_ZERO;
out_mut_sel = `OUT_ZERO;
team_toggle = 1'b1;
if(team_active)
inning_mut_sel = `INNING_PLUSONE;
end
if(got_strike)
strike_mut_sel = `STRIKE_PLUSONE;
if(got_ball)
ball_mut_sel = `BALL_PLUSONE;
if(got_foul && strike_count < 2)
strike_mut_sel = `STRIKE_PLUSONE;
if(got_hit) begin
strike_mut_sel = `STRIKE_ZERO;
ball_mut_sel = `BALL_ZERO;
end
if(got_out) begin
strike_mut_sel = `STRIKE_ZERO;
ball_mut_sel = `BALL_ZERO;
out_mut_sel = `OUT_PLUSONE;
end
end
end
endmodule