first commit
This commit is contained in:
28
README.TXT
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28
README.TXT
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@@ -0,0 +1,28 @@
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Baseball Scoreboard
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- PR 2025
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Project to practice SystemVerilog and FPGA design flow in Vivado.
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Let's play ball! The design keeps track of strikes, balls, outs, and the current
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inning of a baseball game. For the Basys3 board, this is how it looks:
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LEDs : IIII_T_SS_BBB_OO
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IIII = current inning, in binary
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T = team at bat (top or bottom inning)
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SS = strike tally count
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BBB = ball tally count
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OO = out tally count
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The operator inputs the result of the pitch using the face buttons:
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( HIT )
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( STRIKE ) ( OUT ) ( BALL )
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( FOUL)
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Switch 0 (right-most) resets the circuit when asserted.
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The simulate; go into the `sim` directory and run `run_iverilog.cmd`;
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then use `vvp output/baseball_testbench.vvp` to create the waveform dump.
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To synthesize the design for the Basys3 board; run `start_vivado_cli.cmd` from
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the `vivado_flow` directory; then in the TCL console use `source run_batch.tcl`.
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74
rtl/baseball_controlpath.sv
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74
rtl/baseball_controlpath.sv
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`include "constants.sv"
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module baseball_controlpath (
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input logic got_strike,
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input logic got_ball,
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input logic got_foul,
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input logic got_hit,
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input logic got_out,
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input logic strikeout,
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input logic walk,
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input logic three_outs,
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input logic game_ended,
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input logic [1:0] strike_count,
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input logic team_active,
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output logic [1:0] strike_mut_sel,
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output logic [1:0] ball_mut_sel,
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output logic [1:0] out_mut_sel,
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output logic inning_mut_sel,
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output logic team_toggle
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);
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always_comb begin
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strike_mut_sel = `STRIKE_NOCHANGE;
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ball_mut_sel = `BALL_NOCHANGE;
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out_mut_sel = `OUT_NOCHANGE;
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inning_mut_sel = `INNING_NOCHANGE;
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team_toggle = 1'b0;
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if(!game_ended) begin
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if(strikeout) begin
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strike_mut_sel = `STRIKE_ZERO;
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ball_mut_sel = `BALL_ZERO;
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out_mut_sel = `OUT_PLUSONE;
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end
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if(walk) begin
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strike_mut_sel = `STRIKE_ZERO;
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ball_mut_sel = `BALL_ZERO;
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end
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if(three_outs) begin
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strike_mut_sel = `STRIKE_ZERO;
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ball_mut_sel = `BALL_ZERO;
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out_mut_sel = `OUT_ZERO;
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team_toggle = 1'b1;
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if(team_active)
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inning_mut_sel = `INNING_PLUSONE;
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end
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if(got_strike)
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strike_mut_sel = `STRIKE_PLUSONE;
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if(got_ball)
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ball_mut_sel = `BALL_PLUSONE;
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if(got_foul && strike_count < 2)
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strike_mut_sel = `STRIKE_PLUSONE;
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if(got_hit) begin
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strike_mut_sel = `STRIKE_ZERO;
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ball_mut_sel = `BALL_ZERO;
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end
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if(got_out) begin
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strike_mut_sel = `STRIKE_ZERO;
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ball_mut_sel = `BALL_ZERO;
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out_mut_sel = `OUT_PLUSONE;
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end
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end
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end
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endmodule
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115
rtl/baseball_datapath.sv
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115
rtl/baseball_datapath.sv
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module baseball_datapath (
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input logic clock,
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input logic reset,
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input logic [1:0] strike_mut_sel,
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input logic [1:0] ball_mut_sel,
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input logic [1:0] out_mut_sel,
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input logic inning_mut_sel,
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input logic team_toggle,
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output logic strikeout,
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output logic walk,
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output logic three_outs,
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output logic game_ended,
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output logic [1:0] strike_count,
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output logic [2:0] ball_count,
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output logic [1:0] out_count,
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output logic [3:0] inning_count,
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output logic team_active
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);
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logic [1:0] strike_next;
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logic [2:0] ball_next;
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logic [1:0] out_next;
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logic [3:0] inning_next;
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logic team_next;
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assign strikeout = (strike_count >= 3);
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assign walk = (ball_count >= 4);
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assign three_outs = (out_count >= 3);
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assign game_ended = (inning_count >= 10);
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multiplexer4 #(.WIDTH(2)) strike_mut (
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.sel(strike_mut_sel),
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.in0(strike_count),
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.in1('b0),
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.in2(strike_count + 1),
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.in3('bx),
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.out(strike_next)
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);
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multiplexer4 #(.WIDTH(3)) ball_mut (
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.sel(ball_mut_sel),
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.in0(ball_count),
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.in1('b0),
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.in2(ball_count + 1),
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.in3('bx),
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.out(ball_next)
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);
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multiplexer4 #(.WIDTH(2)) out_mut (
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.sel(out_mut_sel),
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.in0(out_count),
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.in1('b0),
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.in2(out_count + 1),
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.in3('bx),
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.out(out_next)
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);
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multiplexer2 #(.WIDTH(4)) inning_mut (
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.sel(inning_mut_sel),
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.in0(inning_count),
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.in1(inning_count + 1),
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.out(inning_next)
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);
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multiplexer2 #(.WIDTH(1)) team_mut (
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.sel(team_toggle),
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.in0(team_active),
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.in1(~team_active),
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.out(team_next)
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);
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register #(.WIDTH(2)) strike_register (
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.clock(clock),
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.reset(reset),
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.write_en('1),
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.next(strike_next),
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.value(strike_count)
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);
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register #(.WIDTH(3)) ball_register (
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.clock(clock),
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.reset(reset),
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.write_en('1),
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.next(ball_next),
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.value(ball_count)
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);
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register #(.WIDTH(2)) out_register (
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.clock(clock),
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.reset(reset),
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.write_en('1),
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.next(out_next),
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.value(out_count)
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);
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register #(.WIDTH(4), .RESET(1)) inning_register (
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.clock(clock),
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.reset(reset),
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.write_en('1),
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.next(inning_next),
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.value(inning_count)
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);
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register #(.WIDTH(1)) team_register (
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.clock(clock),
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.reset(reset),
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.write_en('1),
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.next(team_next),
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.value(team_active)
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);
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endmodule
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65
rtl/baseball_scoreboard.sv
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65
rtl/baseball_scoreboard.sv
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@@ -0,0 +1,65 @@
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module baseball_scoreboard (
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input logic clock,
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input logic reset,
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input logic got_strike,
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input logic got_ball,
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input logic got_foul,
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input logic got_hit,
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input logic got_out,
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output logic [1:0] strike_count,
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output logic [2:0] ball_count,
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output logic [1:0] out_count,
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output logic [3:0] inning_count,
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output logic team_active
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);
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logic [1:0] strike_mut_sel;
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logic [1:0] ball_mut_sel;
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logic [1:0] out_mut_sel;
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logic inning_mut_sel;
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logic team_toggle;
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logic strikeout;
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logic walk;
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logic three_outs;
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logic game_ended;
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baseball_controlpath ctlpath (
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.got_strike(got_strike),
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.got_ball(got_ball),
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.got_foul(got_foul),
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.got_hit(got_hit),
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.got_out(got_out),
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.strikeout(strikeout),
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.walk(walk),
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.three_outs(three_outs),
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.game_ended(game_ended),
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.strike_count(strike_count),
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.team_active(team_active),
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.strike_mut_sel(strike_mut_sel),
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.ball_mut_sel(ball_mut_sel),
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.out_mut_sel(out_mut_sel),
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.inning_mut_sel(inning_mut_sel),
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.team_toggle(team_toggle)
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);
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baseball_datapath datapath (
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.clock(clock),
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.reset(reset),
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.strike_mut_sel(strike_mut_sel),
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.ball_mut_sel(ball_mut_sel),
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.out_mut_sel(out_mut_sel),
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.inning_mut_sel(inning_mut_sel),
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.team_toggle(team_toggle),
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.strikeout(strikeout),
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.walk(walk),
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.three_outs(three_outs),
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.game_ended(game_ended),
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.strike_count(strike_count),
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.ball_count(ball_count),
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.out_count(out_count),
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.inning_count(inning_count),
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.team_active(team_active)
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);
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endmodule
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92
rtl/basys3_toplevel.sv
Normal file
92
rtl/basys3_toplevel.sv
Normal file
@@ -0,0 +1,92 @@
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module basys3_toplevel (
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input logic clk,
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input logic btnC,
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input logic btnU,
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input logic btnL,
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input logic btnR,
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input logic btnD,
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input logic [15:0] sw,
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output logic [15:0] led
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);
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logic clock;
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logic reset;
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assign clock = clk;
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assign reset = sw[0];
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logic got_strike;
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logic got_ball;
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logic got_foul;
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logic got_hit;
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logic got_out;
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logic [1:0] strike_count;
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logic [2:0] ball_count;
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logic [1:0] out_count;
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logic [3:0] inning_count;
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logic team_active;
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assign led[15:12] = inning_count;
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assign led[11] = 'b0;
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assign led[10] = team_active;
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assign led[9] = 'b0;
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assign led[8] = (strike_count > 0);
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assign led[7] = (strike_count > 1);
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assign led[6] = 'b0;
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assign led[5] = (ball_count > 0);
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assign led[4] = (ball_count > 1);
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assign led[3] = (ball_count > 2);
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assign led[2] = 'b0;
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assign led[1] = (out_count > 0);
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assign led[0] = (out_count > 1);
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button_trigger btnC_trigger (
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.clock(clock),
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.reset(reset),
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.raw_button(btnC),
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.trigger_signal(got_out)
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);
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button_trigger btnU_trigger (
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.clock(clock),
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.reset(reset),
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.raw_button(btnU),
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.trigger_signal(got_hit)
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);
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button_trigger btnL_trigger (
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.clock(clock),
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.reset(reset),
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.raw_button(btnL),
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.trigger_signal(got_strike)
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);
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button_trigger btnR_trigger (
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.clock(clock),
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.reset(reset),
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.raw_button(btnR),
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.trigger_signal(got_ball)
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);
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button_trigger btnD_trigger (
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.clock(clock),
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.reset(reset),
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.raw_button(btnD),
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.trigger_signal(got_foul)
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);
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baseball_scoreboard baseball(
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.clock(clock),
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.reset(reset),
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.got_strike(got_strike),
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.got_ball(got_ball),
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.got_foul(got_foul),
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.got_hit(got_hit),
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.got_out(got_out),
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.strike_count(strike_count),
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.ball_count(ball_count),
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.out_count(out_count),
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.inning_count(inning_count),
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.team_active(team_active)
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);
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endmodule
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49
rtl/button_trigger.sv
Normal file
49
rtl/button_trigger.sv
Normal file
@@ -0,0 +1,49 @@
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module button_trigger # (
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parameter CLOCK_FREQUENCY = 100_000_000,
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parameter DEBOUNCE_MILLIS = 40
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) (
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input logic clock,
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input logic reset,
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input logic raw_button,
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output logic trigger_signal
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);
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localparam DEBOUNCE_COUNTER_MAX = (CLOCK_FREQUENCY / 1000) * DEBOUNCE_MILLIS;
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logic [$clog2(DEBOUNCE_COUNTER_MAX)-1:0] counter;
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enum logic [1:0] { ST_IDLE, ST_FILTER, ST_RELEASE } state;
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always_ff @(posedge clock, posedge reset) begin
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if(reset) begin
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state <= ST_IDLE;
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counter <= 'bx;
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trigger_signal <= '0;
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end else case(state)
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ST_IDLE: begin
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if(raw_button) begin
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counter <= DEBOUNCE_COUNTER_MAX;
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state <= ST_FILTER;
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end
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end
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ST_FILTER: begin
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if(!raw_button)
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state <= ST_IDLE;
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else if(counter > 0)
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counter <= counter - 1;
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else begin
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trigger_signal <= '1;
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state <= ST_RELEASE;
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end
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end
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ST_RELEASE: begin
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trigger_signal <= '0;
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if(!raw_button)
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state <= ST_IDLE;
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end
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default: state <= ST_IDLE;
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endcase
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end
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endmodule
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19
rtl/common/multiplexer.sv
Normal file
19
rtl/common/multiplexer.sv
Normal file
@@ -0,0 +1,19 @@
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module multiplexer #(
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parameter WIDTH = 32,
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parameter CHANNELS = 2
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) (
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input logic [$clog2(CHANNELS)-1:0] sel,
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input logic [(CHANNELS*WIDTH)-1:0] in_bus,
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output logic [WIDTH-1:0] out
|
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);
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genvar ig;
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logic [WIDTH-1:0] in_array [CHANNELS];
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assign out = in_array[sel];
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for(ig = 0; ig < CHANNELS; ig = ig + 1) begin
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assign in_array[(CHANNELS - 1) - ig] = in_bus[ig * WIDTH +: WIDTH];
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end
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||||
endmodule
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16
rtl/common/multiplexer2.sv
Normal file
16
rtl/common/multiplexer2.sv
Normal file
@@ -0,0 +1,16 @@
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module multiplexer2 #(
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||||
parameter WIDTH = 32
|
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) (
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||||
input logic sel,
|
||||
input logic [WIDTH-1:0] in0,
|
||||
input logic [WIDTH-1:0] in1,
|
||||
output logic [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
multiplexer #(.WIDTH(WIDTH), .CHANNELS(2)) multiplexer_inst (
|
||||
.sel(sel),
|
||||
.in_bus({in0, in1}),
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.out(out)
|
||||
);
|
||||
|
||||
endmodule
|
||||
18
rtl/common/multiplexer4.sv
Normal file
18
rtl/common/multiplexer4.sv
Normal file
@@ -0,0 +1,18 @@
|
||||
module multiplexer4 #(
|
||||
parameter WIDTH = 32
|
||||
) (
|
||||
input logic [1:0] sel,
|
||||
input logic [WIDTH-1:0] in0,
|
||||
input logic [WIDTH-1:0] in1,
|
||||
input logic [WIDTH-1:0] in2,
|
||||
input logic [WIDTH-1:0] in3,
|
||||
output logic [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
multiplexer #(.WIDTH(WIDTH), .CHANNELS(4)) multiplexer_inst (
|
||||
.sel(sel),
|
||||
.in_bus({in0, in1, in2, in3}),
|
||||
.out(out)
|
||||
);
|
||||
|
||||
endmodule
|
||||
18
rtl/common/register.sv
Normal file
18
rtl/common/register.sv
Normal file
@@ -0,0 +1,18 @@
|
||||
module register #(
|
||||
parameter WIDTH = 32,
|
||||
parameter RESET = 0
|
||||
) (
|
||||
input logic clock,
|
||||
input logic reset,
|
||||
input logic write_en,
|
||||
input logic [WIDTH-1:0] next,
|
||||
output logic [WIDTH-1:0] value
|
||||
);
|
||||
|
||||
always_ff @(posedge clock, posedge reset)
|
||||
if(reset)
|
||||
value <= RESET;
|
||||
else if(write_en)
|
||||
value <= next;
|
||||
|
||||
endmodule
|
||||
21
rtl/constants.sv
Normal file
21
rtl/constants.sv
Normal file
@@ -0,0 +1,21 @@
|
||||
`define EVENT_NONE 3'h0
|
||||
`define EVENT_STRIKE 3'h1
|
||||
`define EVENT_BALL 3'h2
|
||||
`define EVENT_FOUL 3'h3
|
||||
`define EVENT_HIT 3'h4
|
||||
`define EVENT_OUT 3'h5
|
||||
|
||||
`define STRIKE_NOCHANGE 2'b00
|
||||
`define STRIKE_ZERO 2'b01
|
||||
`define STRIKE_PLUSONE 2'b10
|
||||
|
||||
`define BALL_NOCHANGE 2'b00
|
||||
`define BALL_ZERO 2'b01
|
||||
`define BALL_PLUSONE 2'b10
|
||||
|
||||
`define OUT_NOCHANGE 2'b00
|
||||
`define OUT_ZERO 2'b01
|
||||
`define OUT_PLUSONE 2'b10
|
||||
|
||||
`define INNING_NOCHANGE 1'b0
|
||||
`define INNING_PLUSONE 1'b1
|
||||
76
sim/baseball_testbench.sv
Normal file
76
sim/baseball_testbench.sv
Normal file
@@ -0,0 +1,76 @@
|
||||
`timescale 1ns/1ns
|
||||
|
||||
module baseball_testbench ();
|
||||
|
||||
logic clock;
|
||||
logic reset;
|
||||
initial clock = 0;
|
||||
initial reset = 0;
|
||||
always #1 clock = ~clock;
|
||||
|
||||
logic got_strike;
|
||||
logic got_ball;
|
||||
logic got_foul;
|
||||
logic got_hit;
|
||||
logic got_out;
|
||||
logic [1:0] strike_count;
|
||||
logic [2:0] ball_count;
|
||||
logic [1:0] out_count;
|
||||
logic [3:0] inning_count;
|
||||
logic team_active;
|
||||
|
||||
baseball_scoreboard uut(
|
||||
.clock(clock),
|
||||
.reset(reset),
|
||||
.got_strike(got_strike),
|
||||
.got_ball(got_ball),
|
||||
.got_foul(got_foul),
|
||||
.got_hit(got_hit),
|
||||
.got_out(got_out),
|
||||
.strike_count(strike_count),
|
||||
.ball_count(ball_count),
|
||||
.out_count(out_count),
|
||||
.inning_count(inning_count),
|
||||
.team_active(team_active)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("output/baseball_testbench.vcd");
|
||||
$dumpvars(0, baseball_testbench);
|
||||
|
||||
got_strike = 0;
|
||||
got_ball = 0;
|
||||
got_foul = 0;
|
||||
got_hit = 0;
|
||||
got_out = 0;
|
||||
|
||||
@(negedge clock) reset <= '1;
|
||||
@(negedge clock) reset <= '0;
|
||||
|
||||
repeat (9) begin
|
||||
@(negedge clock) got_strike <= '1;
|
||||
@(negedge clock) got_strike <= '0;
|
||||
end
|
||||
|
||||
repeat (5) begin
|
||||
@(negedge clock) got_foul <= '1;
|
||||
@(negedge clock) got_foul <= '0;
|
||||
end
|
||||
|
||||
@(negedge clock) got_strike <= '1;
|
||||
@(negedge clock) got_strike <= '0;
|
||||
|
||||
repeat (2) begin
|
||||
@(negedge clock) got_strike <= '1;
|
||||
@(negedge clock) got_strike <= '0;
|
||||
end
|
||||
|
||||
repeat (4) begin
|
||||
@(negedge clock) got_ball <= '1;
|
||||
@(negedge clock) got_ball <= '0;
|
||||
end
|
||||
|
||||
#10 $finish();
|
||||
end
|
||||
|
||||
endmodule
|
||||
13
sim/run_iverilog.cmd
Normal file
13
sim/run_iverilog.cmd
Normal file
@@ -0,0 +1,13 @@
|
||||
mkdir output
|
||||
|
||||
iverilog -g2012 ^
|
||||
-tvvp ^
|
||||
-I../rtl/ ^
|
||||
-Y.sv ^
|
||||
-y../rtl/common ^
|
||||
-s baseball_testbench ^
|
||||
-ooutput/baseball_testbench.vvp ^
|
||||
baseball_testbench.sv ^
|
||||
../rtl/baseball_scoreboard.sv ^
|
||||
../rtl/baseball_controlpath.sv ^
|
||||
../rtl/baseball_datapath.sv
|
||||
295
vivado_flow/Basys3_Master.xdc
Normal file
295
vivado_flow/Basys3_Master.xdc
Normal file
@@ -0,0 +1,295 @@
|
||||
## This file is a general .xdc for the Basys3 rev B board
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
# Clock signal
|
||||
set_property PACKAGE_PIN W5 [get_ports clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk]
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
|
||||
|
||||
# Switches
|
||||
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
|
||||
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
|
||||
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
|
||||
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
|
||||
set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
|
||||
set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
|
||||
set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
|
||||
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
|
||||
set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
|
||||
set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
|
||||
set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
|
||||
set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
|
||||
set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
|
||||
set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
|
||||
set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
|
||||
set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
|
||||
|
||||
|
||||
# LEDs
|
||||
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
|
||||
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
|
||||
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
|
||||
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
|
||||
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
|
||||
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
|
||||
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
|
||||
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
|
||||
set_property PACKAGE_PIN V13 [get_ports {led[8]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
|
||||
set_property PACKAGE_PIN V3 [get_ports {led[9]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
|
||||
set_property PACKAGE_PIN W3 [get_ports {led[10]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
|
||||
set_property PACKAGE_PIN U3 [get_ports {led[11]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
|
||||
set_property PACKAGE_PIN P3 [get_ports {led[12]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
|
||||
set_property PACKAGE_PIN N3 [get_ports {led[13]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
|
||||
set_property PACKAGE_PIN P1 [get_ports {led[14]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
|
||||
set_property PACKAGE_PIN L1 [get_ports {led[15]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
|
||||
|
||||
|
||||
##7 segment display
|
||||
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
|
||||
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
|
||||
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
|
||||
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
|
||||
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
|
||||
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
|
||||
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
|
||||
|
||||
#set_property PACKAGE_PIN V7 [get_ports dp]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
|
||||
|
||||
#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
|
||||
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
|
||||
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
|
||||
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
|
||||
|
||||
|
||||
#Buttons
|
||||
set_property PACKAGE_PIN U18 [get_ports btnC]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports btnC]
|
||||
set_property PACKAGE_PIN T18 [get_ports btnU]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports btnU]
|
||||
set_property PACKAGE_PIN W19 [get_ports btnL]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports btnL]
|
||||
set_property PACKAGE_PIN T17 [get_ports btnR]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports btnR]
|
||||
set_property PACKAGE_PIN U17 [get_ports btnD]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports btnD]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
##Sch name = JA1
|
||||
#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
|
||||
##Sch name = JA2
|
||||
#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
|
||||
##Sch name = JA3
|
||||
#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
|
||||
##Sch name = JA4
|
||||
#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
|
||||
##Sch name = JA7
|
||||
#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
|
||||
##Sch name = JA8
|
||||
#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
|
||||
##Sch name = JA9
|
||||
#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
|
||||
##Sch name = JA10
|
||||
#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
##Sch name = JB1
|
||||
#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
|
||||
##Sch name = JB2
|
||||
#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
|
||||
##Sch name = JB3
|
||||
#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
|
||||
##Sch name = JB4
|
||||
#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
|
||||
##Sch name = JB7
|
||||
#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
|
||||
##Sch name = JB8
|
||||
#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
|
||||
##Sch name = JB9
|
||||
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
|
||||
##Sch name = JB10
|
||||
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
##Sch name = JC1
|
||||
#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
|
||||
##Sch name = JC2
|
||||
#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
|
||||
##Sch name = JC3
|
||||
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
|
||||
##Sch name = JC4
|
||||
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
|
||||
##Sch name = JC7
|
||||
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
|
||||
##Sch name = JC8
|
||||
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
|
||||
##Sch name = JC9
|
||||
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
|
||||
##Sch name = JC10
|
||||
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
##Sch name = XA1_P
|
||||
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
|
||||
##Sch name = XA2_P
|
||||
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
|
||||
##Sch name = XA3_P
|
||||
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
|
||||
##Sch name = XA4_P
|
||||
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
|
||||
##Sch name = XA1_N
|
||||
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
|
||||
##Sch name = XA2_N
|
||||
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
|
||||
##Sch name = XA3_N
|
||||
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
|
||||
##Sch name = XA4_N
|
||||
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
|
||||
|
||||
|
||||
|
||||
##VGA Connector
|
||||
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
|
||||
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
|
||||
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
|
||||
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
|
||||
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
|
||||
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
|
||||
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
|
||||
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
|
||||
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
|
||||
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
|
||||
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
|
||||
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
|
||||
#set_property PACKAGE_PIN P19 [get_ports Hsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
|
||||
#set_property PACKAGE_PIN R19 [get_ports Vsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property PACKAGE_PIN B18 [get_ports RsRx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
|
||||
#set_property PACKAGE_PIN A18 [get_ports RsTx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
|
||||
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
|
||||
#set_property PULLUP true [get_ports PS2Clk]
|
||||
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
|
||||
#set_property PULLUP true [get_ports PS2Data]
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
|
||||
##STARTUPE2 primitive.
|
||||
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
|
||||
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
|
||||
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
|
||||
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
|
||||
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
|
||||
|
||||
28
vivado_flow/run_batch.tcl
Normal file
28
vivado_flow/run_batch.tcl
Normal file
@@ -0,0 +1,28 @@
|
||||
set PROJECT_DIR ..
|
||||
set OUTPUT_DIR ./output
|
||||
set PART_NO xc7a35tcpg236-1
|
||||
|
||||
file mkdir $OUTPUT_DIR
|
||||
|
||||
read_verilog [ glob $PROJECT_DIR/rtl/*.sv ]
|
||||
read_verilog [ glob $PROJECT_DIR/rtl/common/*.sv ]
|
||||
read_xdc $PROJECT_DIR/vivado_flow/Basys3_Master.xdc
|
||||
|
||||
synth_design -top basys3_toplevel -part $PART_NO -include_dirs $PROJECT_DIR/rtl
|
||||
report_timing_summary -file $OUTPUT_DIR/post_synth_timing_summary.rpt
|
||||
report_power -file $OUTPUT_DIR/post_synth_power.rpt
|
||||
|
||||
opt_design
|
||||
place_design
|
||||
phys_opt_design
|
||||
report_timing_summary -file $OUTPUT_DIR/post_place_timing_summary.rpt
|
||||
|
||||
route_design
|
||||
report_timing -sort_by group -max_paths 100 -path_type summary -file $OUTPUT_DIR/post_route_timing.rpt
|
||||
report_timing_summary -file $OUTPUT_DIR/post_route_timing_summary.rpt
|
||||
report_clock_utilization -file $OUTPUT_DIR/clock_util.rpt
|
||||
report_utilization -file $OUTPUT_DIR/post_route_util.rpt
|
||||
report_power -file $OUTPUT_DIR/post_route_power.rpt
|
||||
report_drc -file $OUTPUT_DIR/post_imp_drc.rpt
|
||||
|
||||
write_bitstream -force $OUTPUT_DIR/$PART_NO.bit
|
||||
3
vivado_flow/start_vivado_cli.cmd
Normal file
3
vivado_flow/start_vivado_cli.cmd
Normal file
@@ -0,0 +1,3 @@
|
||||
call D:\Dev\Xilinx\Vivado\2024.1\bin\vivado.bat -mode tcl
|
||||
del *.jou
|
||||
del *.log
|
||||
Reference in New Issue
Block a user