2025-04-06 00:11:28 -04:00
2025-04-06 00:11:28 -04:00
2025-04-06 00:11:28 -04:00
2025-04-06 00:11:28 -04:00
2025-04-06 00:11:28 -04:00

Baseball Scoreboard
	- PR 2025

Project to practice SystemVerilog and FPGA design flow in Vivado.

Let's play ball! The design keeps track of strikes, balls, outs, and the current
inning of a baseball game. For the Basys3 board, this is how it looks:

LEDs : IIII_T_SS_BBB_OO
	IIII = current inning, in binary
	T    = team at bat (top or bottom inning)
	SS   = strike tally count
	BBB  = ball tally count
	OO   = out tally count

The operator inputs the result of the pitch using the face buttons:

            ( HIT )
( STRIKE )  ( OUT )  ( BALL )
            ( FOUL)
			
Switch 0 (right-most) resets the circuit when asserted.

The simulate; go into the `sim` directory and run `run_iverilog.cmd`;
then use `vvp output/baseball_testbench.vvp` to create the waveform dump.

To synthesize the design for the Basys3 board; run `start_vivado_cli.cmd` from
the `vivado_flow` directory; then in the TCL console use `source run_batch.tcl`.
Description
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Readme 34 KiB
Languages
Tcl 53.9%
SystemVerilog 44.8%
Batchfile 1.3%