19 lines
422 B
Systemverilog
19 lines
422 B
Systemverilog
module multiplexer #(
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parameter WIDTH = 32,
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parameter CHANNELS = 2
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) (
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input logic [$clog2(CHANNELS)-1:0] sel,
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input logic [(CHANNELS*WIDTH)-1:0] in_bus,
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output logic [WIDTH-1:0] out
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);
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genvar ig;
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logic [WIDTH-1:0] in_array [CHANNELS];
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assign out = in_array[sel];
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for(ig = 0; ig < CHANNELS; ig = ig + 1) begin
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assign in_array[(CHANNELS - 1) - ig] = in_bus[ig * WIDTH +: WIDTH];
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end
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endmodule |