16 lines
302 B
Systemverilog
16 lines
302 B
Systemverilog
module multiplexer2 #(
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parameter WIDTH = 32
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) (
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input logic sel,
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input logic [WIDTH-1:0] in0,
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input logic [WIDTH-1:0] in1,
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output logic [WIDTH-1:0] out
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);
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multiplexer #(.WIDTH(WIDTH), .CHANNELS(2)) multiplexer_inst (
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.sel(sel),
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.in_bus({in0, in1}),
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.out(out)
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);
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endmodule |