18 lines
359 B
Systemverilog
18 lines
359 B
Systemverilog
module register #(
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parameter WIDTH = 32,
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parameter RESET = 0
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) (
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input logic clock,
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input logic reset,
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input logic write_en,
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input logic [WIDTH-1:0] next,
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output logic [WIDTH-1:0] value
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);
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always_ff @(posedge clock, posedge reset)
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if(reset)
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value <= RESET;
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else if(write_en)
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value <= next;
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endmodule |