49 lines
1014 B
Systemverilog
49 lines
1014 B
Systemverilog
module button_trigger # (
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parameter CLOCK_FREQUENCY = 100_000_000,
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parameter DEBOUNCE_MILLIS = 40
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) (
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input logic clock,
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input logic reset,
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input logic raw_button,
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output logic trigger_signal
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);
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localparam DEBOUNCE_COUNTER_MAX = (CLOCK_FREQUENCY / 1000) * DEBOUNCE_MILLIS;
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logic [$clog2(DEBOUNCE_COUNTER_MAX)-1:0] counter;
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enum logic [1:0] { ST_IDLE, ST_FILTER, ST_RELEASE } state;
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always_ff @(posedge clock, posedge reset) begin
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if(reset) begin
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state <= ST_IDLE;
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counter <= 'bx;
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trigger_signal <= '0;
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end else case(state)
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ST_IDLE: begin
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if(raw_button) begin
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counter <= DEBOUNCE_COUNTER_MAX;
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state <= ST_FILTER;
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end
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end
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ST_FILTER: begin
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if(!raw_button)
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state <= ST_IDLE;
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else if(counter > 0)
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counter <= counter - 1;
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else begin
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trigger_signal <= '1;
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state <= ST_RELEASE;
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end
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end
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ST_RELEASE: begin
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trigger_signal <= '0;
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if(!raw_button)
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state <= ST_IDLE;
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end
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default: state <= ST_IDLE;
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endcase
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end
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endmodule |