76 lines
1.4 KiB
Systemverilog
76 lines
1.4 KiB
Systemverilog
`timescale 1ns/1ns
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module baseball_testbench ();
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logic clock;
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logic reset;
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initial clock = 0;
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initial reset = 0;
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always #1 clock = ~clock;
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logic got_strike;
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logic got_ball;
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logic got_foul;
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logic got_hit;
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logic got_out;
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logic [1:0] strike_count;
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logic [2:0] ball_count;
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logic [1:0] out_count;
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logic [3:0] inning_count;
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logic team_active;
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baseball_scoreboard uut(
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.clock(clock),
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.reset(reset),
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.got_strike(got_strike),
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.got_ball(got_ball),
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.got_foul(got_foul),
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.got_hit(got_hit),
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.got_out(got_out),
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.strike_count(strike_count),
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.ball_count(ball_count),
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.out_count(out_count),
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.inning_count(inning_count),
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.team_active(team_active)
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);
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initial begin
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$dumpfile("output/baseball_testbench.vcd");
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$dumpvars(0, baseball_testbench);
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got_strike = 0;
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got_ball = 0;
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got_foul = 0;
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got_hit = 0;
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got_out = 0;
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@(negedge clock) reset <= '1;
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@(negedge clock) reset <= '0;
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repeat (9) begin
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@(negedge clock) got_strike <= '1;
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@(negedge clock) got_strike <= '0;
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end
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repeat (5) begin
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@(negedge clock) got_foul <= '1;
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@(negedge clock) got_foul <= '0;
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end
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@(negedge clock) got_strike <= '1;
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@(negedge clock) got_strike <= '0;
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repeat (2) begin
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@(negedge clock) got_strike <= '1;
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@(negedge clock) got_strike <= '0;
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end
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repeat (4) begin
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@(negedge clock) got_ball <= '1;
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@(negedge clock) got_ball <= '0;
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end
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#10 $finish();
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end
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endmodule |