33 lines
1.2 KiB
Plaintext
33 lines
1.2 KiB
Plaintext
Video Card
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- PR 2025
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Project to practice Verilog and FPGA design flow in Vivado.
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The design will display a static image to a monitor via the VGA
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port of the Basys3 board. For demonstration purposes an LED light
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and the seven segment display also light up. The image is stored
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in the FPGA's block RAM, it can be customized by using the Python
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script provided in the tools directory to convert any image file
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you want to display:
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python3 tools/main.py input.png > init/vram.init
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To simulate; go into the `sim` directory and run `make`;
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then use `vvp output/testbench.vvp` to create the waveform dump.
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To synthesize the design for the Basys3 board; enter the `vivado_flow` directory
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and run `vivado -mode batch -source run_batch.tcl`. This will create the bitstream
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file to program the FPGA.
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Basys3 resources:
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Diligent reference manual:
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https://digilent.com/reference/programmable-logic/basys-3/reference-manual
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Xilinx Vivado resources:
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Block RAM and HDL coding techniques:
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https://docs.amd.com/r/en-US/ug901-vivado-synthesis/Single-Port-Block-RAM-with-Resettable-Data-Output-Verilog
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Design flow with Tcl scripts:
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https://docs.amd.com/r/en-US/ug894-vivado-tcl-scripting/Compilation-with-a-Non-Project-Flow
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