first commit

.gitattributes

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+*.jpg binary
+*.bit binary

.gitignore

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+/tools/.env/**
+/sim/output/**
+/vivado_flow/output/**
+/vivado_flow/.Xil/**
+/vivado_flow/*.jou
+/vivado_flow/*.log
+/vivado_flow/clockInfo.txt

README.TXT

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+Video Card
+	- PR 2025
+
+Project to practice Verilog and FPGA design flow in Vivado.
+
+The design will display a static image to a monitor via the VGA
+port of the Basys3 board. For demonstration purposes an LED light
+and the seven segment display also light up. The image is stored
+in the FPGA's block RAM, it can be customized by using the Python
+script provided in the tools directory to convert any image file
+you want to display:
+	python3 tools/main.py input.png > init/vram.init
+
+To simulate; go into the `sim` directory and run `make`;
+then use `vvp output/testbench.vvp` to create the waveform dump.
+
+To synthesize the design for the Basys3 board; enter the `vivado_flow` directory
+and run `vivado -mode batch -source run_batch.tcl`. This will create the bitstream
+file to program the FPGA.
+
+Basys3 resources:
+
+  Diligent reference manual:
+  https://digilent.com/reference/programmable-logic/basys-3/reference-manual
+
+Xilinx Vivado resources:
+
+  Block RAM and HDL coding techniques:
+  https://docs.amd.com/r/en-US/ug901-vivado-synthesis/Single-Port-Block-RAM-with-Resettable-Data-Output-Verilog
+
+  Design flow with Tcl scripts:
+  https://docs.amd.com/r/en-US/ug894-vivado-tcl-scripting/Compilation-with-a-Non-Project-Flow

rtl/Basys3_Top.v

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+module Basys3_Top (
+    input         clk,
+    output [15:0] led,
+    output  [6:0] seg,
+    output  [3:0] an,
+    output        dp,
+    output        Hsync,
+    output        Vsync,
+    output  [3:0] vgaRed,
+    output  [3:0] vgaGreen,
+    output  [3:0] vgaBlue
+);
+    assign led[15:1] = 14'b0;
+    assign dp = 1'b1;
+
+    wire clk_1Hz;
+    wire clk_vga;
+    wire clk_sevseg;
+    
+    Clock_divider clock_divider_1Hz (
+        .clock_in(clk),
+        .clock_out(clk_1Hz)
+    );
+    
+    Clock_divider #(.CLOCK_RATIO(100_000_000/250)) clock_divider_sevseg (
+        .clock_in(clk),
+        .clock_out(clk_sevseg)
+    );
+    
+    Clock_divider #(.CLOCK_RATIO(100_000_000/50_000_000)) clock_divider_vga (
+        .clock_in(clk),
+        .clock_out(clk_vga)
+    );
+    
+    Blinky blinky (
+        .clock(clk),
+        .clock_en(clk_1Hz),
+        .led(led[0])
+    );
+    
+    reg [13:0] counter;
+    wire [1:0] seven_segment_sel;
+    
+    always @(posedge clk) begin
+        if(clk_1Hz)
+            counter <= counter + 1;
+    end
+    
+    Seven_segment_timing seven_segment_timing (
+        .clock(clk),
+        .clock_en(clk_sevseg),
+        .sel(seven_segment_sel),
+        .an(an)
+    );
+    
+    Seven_segment_bcd seven_segment_bcd (
+        .clock(clk),
+        .value(counter),
+        .sel(seven_segment_sel),
+        .seg(seg)
+    );
+    
+    wire [9:0] vga_x, vga_y;
+    wire vga_blank;
+    VGA_timing vga_timing (
+        .clock(clk),
+        .clock_en(clk_vga),
+        .hsync(Hsync),
+        .vsync(Vsync),
+        .blank(vga_blank),
+        .x(vga_x),
+        .y(vga_y)
+    );
+    
+    RAM #(.WIDTH(12), .SIZE(400*300), .INIT_FILENAME("../init/vram.init")) ram (
+        .clock(clk),
+        .reset(vga_blank),
+        .clock_en(clk_vga),
+        .addr(400*vga_y[9:1]+vga_x[9:1]),
+        .din(12'b0),
+        .dout({vgaRed, vgaGreen, vgaBlue})
+    );
+
+endmodule

rtl/Bin2bcd.v

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+// parametric Verilog implementation of the double dabble binary to BCD converter
+// for the complete project, see
+// https://github.com/AmeerAbdelhadi/Binary-to-BCD-Converter
+
+module Bin2bcd
+ #( parameter                W = 18)  // input width
+  ( input      [W-1      :0] bin   ,  // binary
+    output reg [W+(W-4)/3:0] bcd   ); // bcd {...,thousands,hundreds,tens,ones}
+
+  integer i,j;
+
+  always @(bin) begin
+    for(i = 0; i <= W+(W-4)/3; i = i+1) bcd[i] = 0;     // initialize with zeros
+    bcd[W-1:0] = bin;                                   // initialize with input vector
+    for(i = 0; i <= W-4; i = i+1)                       // iterate on structure depth
+      for(j = 0; j <= i/3; j = j+1)                     // iterate on structure width
+        if (bcd[W-i+4*j -: 4] > 4)                      // if > 4
+          bcd[W-i+4*j -: 4] = bcd[W-i+4*j -: 4] + 4'd3; // add 3
+  end
+
+endmodule

rtl/Blinky.v

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+module Blinky (
+    input clock,
+    input clock_en,
+    output reg led
+);
+
+    initial begin
+        led <= 1'b0;
+    end
+
+    always @(posedge clock) begin
+        if(clock_en)
+            led <= ~led;
+    end
+
+endmodule

rtl/Clock_divider.v

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+module Clock_divider #(
+    parameter CLOCK_RATIO = 100_000_000
+) (
+    input      clock_in,
+    output reg clock_out
+);
+    
+    reg [$clog2(CLOCK_RATIO)-1:0] counter;
+    
+    initial begin
+        clock_out = 1'b0;
+        counter = 0;
+    end
+    
+    always @(posedge clock_in) begin
+        clock_out <= (counter >= CLOCK_RATIO-1);
+        counter <= (counter >= CLOCK_RATIO-1 ? 0 : counter + 1);
+    end
+
+endmodule

rtl/RAM.v

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+module RAM #(
+    parameter WIDTH = 8,
+    parameter SIZE  = 128,
+    parameter INIT_FILENAME = ""
+) (
+    input                    clock,
+    input                    reset,
+    input                    clock_en,
+    input                    write_en,
+    input [$clog2(SIZE)-1:0] addr,
+    input        [WIDTH-1:0] din,
+    output reg   [WIDTH-1:0] dout
+);
+
+    reg [WIDTH-1:0] ram[SIZE-1:0], dout;
+    
+    integer i;
+    initial begin
+        if(INIT_FILENAME == "")
+            for(i = 0; i < SIZE; i=i+1) ram[i] = 0;
+        else
+            $readmemb(INIT_FILENAME, ram);
+    end
+    
+    always @(posedge clock) begin
+        if(clock_en) begin
+            dout <= reset ? 0 : ram[addr];
+            if(write_en)
+                ram[addr] <= din;
+        end
+    end
+
+endmodule

rtl/Seven_segment_bcd.v

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+module Seven_segment_bcd(
+    input            clock,
+    input     [13:0] value,
+    input      [1:0] sel,
+    output reg [6:0] seg
+);
+
+    wire [17:0] bcd;
+    wire [3:0]  bcd_digit;
+    
+    initial begin
+        seg = 0;
+    end
+
+    Bin2bcd #(.W(14)) bin2bcd (
+        .bin(value),
+        .bcd(bcd)
+    );
+    
+    assign bcd_digit = bcd[4*sel +: 4];
+    
+    always @(posedge clock) begin
+        case(bcd_digit)
+                     // GFEDCBA
+        4'd0: seg <= 7'b1000000;
+        4'd1: seg <= 7'b1111001;
+        4'd2: seg <= 7'b0100100;
+        4'd3: seg <= 7'b0110000;
+        4'd4: seg <= 7'b0011001;
+        4'd5: seg <= 7'b0010010;
+        4'd6: seg <= 7'b0000010;
+        4'd7: seg <= 7'b1011000;
+        4'd8: seg <= 7'b0000000;
+        4'd9: seg <= 7'b0010000;
+        default: seg <= 7'bx;
+        endcase
+    end
+
+endmodule

rtl/Seven_segment_timing.v

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+module Seven_segment_timing (
+    input            clock,
+    input            clock_en,
+    output reg [1:0] sel,
+    output reg [3:0] an
+);
+
+    initial begin
+        sel = 0;
+        an = 0;
+    end
+    
+    always @(posedge clock) begin
+        an <= ~(4'b0001 << sel);
+        if(clock_en)
+            sel <= sel + 1;
+    end
+
+endmodule

rtl/VGA_timing.v

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+module VGA_timing #(
+    // VESA 800x600@72 use with 50MHz pixel clock
+    parameter H_VISIBLE = 800,  // Visible area
+    parameter H_FRONT   = 56,   // Front porch
+    parameter H_SYNC    = 120,  // Sync pulse
+    parameter H_BACK    = 64,   // Back porch
+    parameter H_TOTAL   = 1040, // Whole line
+    
+    parameter V_VISIBLE = 600, // Visible area
+    parameter V_FRONT   = 37,  // Front porch
+    parameter V_SYNC    = 6,   // Sync pulse
+    parameter V_BACK    = 23,  // Back porch
+    parameter V_TOTAL   = 666  // Whole line
+) (
+    input                            clock,
+    input                            clock_en,
+    output reg                       hsync,
+    output reg                       vsync,
+    output reg                       blank,
+    output reg [$clog2(H_TOTAL)-1:0] x,
+    output reg [$clog2(V_TOTAL)-1:0] y
+);
+    
+    initial begin
+        hsync <= 1'b0;
+        vsync <= 1'b0;
+        blank <= 1'b0;
+        x <= 0;
+        y <= 0;
+    end
+    
+    always @(posedge clock) begin
+        if(clock_en) begin
+            hsync <= ~(H_VISIBLE + H_FRONT <= x && x < H_VISIBLE + H_FRONT + H_SYNC);
+            vsync <= ~(V_VISIBLE + V_FRONT <= y && y < V_VISIBLE + V_FRONT + V_SYNC);
+            blank <= (H_VISIBLE-1 <= x && x < H_VISIBLE-1 + H_FRONT+H_SYNC+H_BACK)
+                  || (V_VISIBLE-1 <= y && y < V_VISIBLE-1 + V_FRONT+V_SYNC+V_BACK);
+            //blank <= (x >= H_VISIBLE-1 || y >= V_VISIBLE-1);
+            if(x >= H_TOTAL-1) begin
+                x <= 0;
+                y <= (y >= V_TOTAL-1) ? 0 : y + 1;
+            end else
+                x <= x + 1;
+        end
+    end
+
+endmodule

sim/Makefile

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+SOURCES = ../rtl/Blinky.v \
+	../rtl/Clock_divider.v \
+	../rtl/Bin2bcd.v \
+	../rtl/Seven_segment_bcd.v \
+	../rtl/Seven_segment_timing.v \
+	../rtl/VGA_timing.v
+
+output/testbench.vvp: testbench.v $(SOURCES)
+	mkdir -p output
+	iverilog -Wall -tvvp -I../rtl -stestbench -o $@ $< $(SOURCES)

sim/testbench.v

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+`timescale 100ps/10ps
+
+module testbench ();
+
+    reg clk;
+    initial clk = 1'b0;
+    always #5 clk = ~clk;
+    
+    wire slow_clk;
+    wire [1:0] segment_select;
+    reg  [13:0] counter;
+    
+    Clock_divider #(.CLOCK_RATIO(4)) clock_divider (
+        .clock_in(clk),
+        .clock_out(slow_clk)
+    );
+    
+    Blinky uut (
+        .clock(clk),
+        .clock_en(slow_clk)
+    );
+    
+    Seven_segment_timing seven_segment_timing (
+        .clock(clk),
+        .sel(segment_select)
+    );
+    
+    Seven_segment_bcd seven_segment_bcd (
+        .clock(clk),
+        .value(counter),
+        .sel(segment_select)
+    );
+    
+    VGA_timing vga (
+        .clock(clk),
+        .clock_en(1'b1)
+    );
+    
+    always @(posedge clk) begin
+        if(slow_clk) counter <= counter + 1;
+    end
+    
+    initial begin
+        $display("Hello, World!");
+        $display("Simulation started.");
+        
+        $dumpfile("output/testbench.vcd");
+        $dumpvars(0, testbench);
+        $display("Writing to output/testbench.vcd");
+        
+        #5000 $finish();
+    end
+
+endmodule

tools/main.py

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+import sys
+from PIL import Image
+
+# Convert an image to a memory initialization file.
+# 400x300@12bpp. Usage: `python3 main.py input.png > output.init`
+def main():
+	im = Image.open(sys.argv[1])
+	im = im.resize((400, 300))
+	im = im.load()
+
+	for pix in ( im[x,y] for y in range(300) for x in range(400) ):
+		r, g, b = map(lambda x: (x >> 4) & 0x0F, pix)
+		print(f'{r:04b}{g:04b}{b:04b}')
+
+	return 0
+
+
+if __name__ == '__main__':
+	sys.exit(main())

tools/requirements.txt

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+pillow==11.3.0

vivado_flow/Basys3_Master.xdc

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+## This file is a general .xdc for the Basys3 rev B board
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+set_property -dict { PACKAGE_PIN W5   IOSTANDARD LVCMOS33 } [get_ports clk]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+
+
+## Switches
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports {sw[0]}]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports {sw[1]}]
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
+#set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports {sw[6]}]
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports {sw[7]}]
+#set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports {sw[8]}]
+#set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
+#set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
+#set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
+#set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
+#set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
+#set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
+#set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]
+
+
+## LEDs
+set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
+set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
+set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports {led[2]}]
+set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports {led[3]}]
+set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports {led[4]}]
+set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports {led[5]}]
+set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports {led[6]}]
+set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports {led[7]}]
+set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports {led[8]}]
+set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports {led[9]}]
+set_property -dict { PACKAGE_PIN W3    IOSTANDARD LVCMOS33 } [get_ports {led[10]}]
+set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports {led[11]}]
+set_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports {led[12]}]
+set_property -dict { PACKAGE_PIN N3    IOSTANDARD LVCMOS33 } [get_ports {led[13]}]
+set_property -dict { PACKAGE_PIN P1    IOSTANDARD LVCMOS33 } [get_ports {led[14]}]
+set_property -dict { PACKAGE_PIN L1    IOSTANDARD LVCMOS33 } [get_ports {led[15]}]
+
+
+##7 Segment Display
+set_property -dict { PACKAGE_PIN W7   IOSTANDARD LVCMOS33 } [get_ports {seg[0]}]
+set_property -dict { PACKAGE_PIN W6   IOSTANDARD LVCMOS33 } [get_ports {seg[1]}]
+set_property -dict { PACKAGE_PIN U8   IOSTANDARD LVCMOS33 } [get_ports {seg[2]}]
+set_property -dict { PACKAGE_PIN V8   IOSTANDARD LVCMOS33 } [get_ports {seg[3]}]
+set_property -dict { PACKAGE_PIN U5   IOSTANDARD LVCMOS33 } [get_ports {seg[4]}]
+set_property -dict { PACKAGE_PIN V5   IOSTANDARD LVCMOS33 } [get_ports {seg[5]}]
+set_property -dict { PACKAGE_PIN U7   IOSTANDARD LVCMOS33 } [get_ports {seg[6]}]
+
+set_property -dict { PACKAGE_PIN V7   IOSTANDARD LVCMOS33 } [get_ports dp]
+
+set_property -dict { PACKAGE_PIN U2   IOSTANDARD LVCMOS33 } [get_ports {an[0]}]
+set_property -dict { PACKAGE_PIN U4   IOSTANDARD LVCMOS33 } [get_ports {an[1]}]
+set_property -dict { PACKAGE_PIN V4   IOSTANDARD LVCMOS33 } [get_ports {an[2]}]
+set_property -dict { PACKAGE_PIN W4   IOSTANDARD LVCMOS33 } [get_ports {an[3]}]
+
+
+##Buttons
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports btnC]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports btnU]
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports btnL]
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports btnR]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports btnD]
+
+
+##Pmod Header JA
+#set_property -dict { PACKAGE_PIN J1   IOSTANDARD LVCMOS33 } [get_ports {JA[0]}];#Sch name = JA1
+#set_property -dict { PACKAGE_PIN L2   IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2
+#set_property -dict { PACKAGE_PIN J2   IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3
+#set_property -dict { PACKAGE_PIN G2   IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4
+#set_property -dict { PACKAGE_PIN H1   IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7
+#set_property -dict { PACKAGE_PIN K2   IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8
+#set_property -dict { PACKAGE_PIN H2   IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9
+#set_property -dict { PACKAGE_PIN G3   IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10
+
+##Pmod Header JB
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2
+#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7
+#set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10
+
+##Pmod Header JXADC
+#set_property -dict { PACKAGE_PIN J3   IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P
+#set_property -dict { PACKAGE_PIN L3   IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P
+#set_property -dict { PACKAGE_PIN M2   IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P
+#set_property -dict { PACKAGE_PIN N2   IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P
+#set_property -dict { PACKAGE_PIN K3   IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N
+#set_property -dict { PACKAGE_PIN M3   IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N
+#set_property -dict { PACKAGE_PIN M1   IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N
+#set_property -dict { PACKAGE_PIN N1   IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N
+
+
+##VGA Connector
+set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}]
+set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}]
+set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}]
+set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}]
+set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}]
+set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}]
+set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}]
+set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}]
+set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}]
+set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}]
+set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}]
+set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}]
+set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports Hsync]
+set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports Vsync]
+
+
+##USB-RS232 Interface
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports RsRx]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports RsTx]
+
+
+##USB HID (PS/2)
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33   PULLUP true } [get_ports PS2Clk]
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33   PULLUP true } [get_ports PS2Data]
+
+
+##Quad SPI Flash
+##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
+##STARTUPE2 primitive.
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}]
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}]
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports QspiCSn]
+
+
+## Configuration options, can be used for all designs
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
+## SPI configuration mode options for QSPI boot, can be used for all designs
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]

vivado_flow/run_batch.tcl

@@ -0,0 +1,30 @@
+set  PROJECT_DIR ..
+set  OUTPUT_DIR  ./output
+set  PART_NO     xc7a35tcpg236-1
+
+file mkdir $OUTPUT_DIR
+
+read_verilog [ glob $PROJECT_DIR/rtl/*.v ]
+read_xdc     $PROJECT_DIR/vivado_flow/Basys3_Master.xdc
+
+synth_design          -top Basys3_Top -part $PART_NO -include_dirs $PROJECT_DIR/rtl
+write_checkpoint      -force $OUTPUT_DIR/post_synth.dcp
+report_timing_summary -file $OUTPUT_DIR/post_synth_timing_summary.rpt
+report_power          -file $OUTPUT_DIR/post_synth_power.rpt
+
+opt_design
+place_design
+phys_opt_design
+write_checkpoint      -force $OUTPUT_DIR/post_place.dcp
+report_timing_summary -file $OUTPUT_DIR/post_place_timing_summary.rpt
+
+route_design
+write_checkpoint         -force $OUTPUT_DIR/post_route.dcp
+report_timing            -sort_by group -max_paths 100 -path_type summary -file $OUTPUT_DIR/post_route_timing.rpt
+report_timing_summary    -file $OUTPUT_DIR/post_route_timing_summary.rpt
+report_clock_utilization -file $OUTPUT_DIR/clock_util.rpt
+report_utilization       -file $OUTPUT_DIR/post_route_util.rpt
+report_power             -file $OUTPUT_DIR/post_route_power.rpt
+report_drc               -file $OUTPUT_DIR/post_imp_drc.rpt
+
+write_bitstream -force $OUTPUT_DIR/$PART_NO.bit

vivado_flow/run_elaborate.tcl

@@ -0,0 +1,11 @@
+set  PROJECT_DIR ..
+set  OUTPUT_DIR  ./output
+set  PART_NO     xc7a35tcpg236-1
+
+file mkdir $OUTPUT_DIR
+
+read_verilog [ glob $PROJECT_DIR/rtl/*.v ]
+read_xdc     $PROJECT_DIR/vivado_flow/Basys3_Master.xdc
+
+synth_design          -top Basys3_Top -rtl -include_dirs $PROJECT_DIR/rtl
+start_gui