40 lines
847 B
Verilog
40 lines
847 B
Verilog
module Seven_segment_bcd(
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input clock,
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input [13:0] value,
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input [1:0] sel,
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output reg [6:0] seg
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);
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wire [17:0] bcd;
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wire [3:0] bcd_digit;
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initial begin
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seg = 0;
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end
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Bin2bcd #(.W(14)) bin2bcd (
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.bin(value),
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.bcd(bcd)
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);
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assign bcd_digit = bcd[4*sel +: 4];
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always @(posedge clock) begin
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case(bcd_digit)
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// GFEDCBA
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4'd0: seg <= 7'b1000000;
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4'd1: seg <= 7'b1111001;
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4'd2: seg <= 7'b0100100;
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4'd3: seg <= 7'b0110000;
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4'd4: seg <= 7'b0011001;
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4'd5: seg <= 7'b0010010;
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4'd6: seg <= 7'b0000010;
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4'd7: seg <= 7'b1011000;
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4'd8: seg <= 7'b0000000;
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4'd9: seg <= 7'b0010000;
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default: seg <= 7'bx;
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endcase
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end
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endmodule
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