22 lines
901 B
Verilog
22 lines
901 B
Verilog
// parametric Verilog implementation of the double dabble binary to BCD converter
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// for the complete project, see
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// https://github.com/AmeerAbdelhadi/Binary-to-BCD-Converter
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module Bin2bcd
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#( parameter W = 18) // input width
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( input [W-1 :0] bin , // binary
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output reg [W+(W-4)/3:0] bcd ); // bcd {...,thousands,hundreds,tens,ones}
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integer i,j;
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always @(bin) begin
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for(i = 0; i <= W+(W-4)/3; i = i+1) bcd[i] = 0; // initialize with zeros
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bcd[W-1:0] = bin; // initialize with input vector
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for(i = 0; i <= W-4; i = i+1) // iterate on structure depth
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for(j = 0; j <= i/3; j = j+1) // iterate on structure width
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if (bcd[W-i+4*j -: 4] > 4) // if > 4
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bcd[W-i+4*j -: 4] = bcd[W-i+4*j -: 4] + 4'd3; // add 3
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end
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endmodule
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