48 lines
1.6 KiB
Verilog
48 lines
1.6 KiB
Verilog
module VGA_timing #(
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// VESA 800x600@72 use with 50MHz pixel clock
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parameter H_VISIBLE = 800, // Visible area
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parameter H_FRONT = 56, // Front porch
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parameter H_SYNC = 120, // Sync pulse
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parameter H_BACK = 64, // Back porch
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parameter H_TOTAL = 1040, // Whole line
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parameter V_VISIBLE = 600, // Visible area
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parameter V_FRONT = 37, // Front porch
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parameter V_SYNC = 6, // Sync pulse
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parameter V_BACK = 23, // Back porch
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parameter V_TOTAL = 666 // Whole line
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) (
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input clock,
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input clock_en,
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output reg hsync,
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output reg vsync,
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output reg blank,
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output reg [$clog2(H_TOTAL)-1:0] x,
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output reg [$clog2(V_TOTAL)-1:0] y
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);
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initial begin
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hsync <= 1'b0;
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vsync <= 1'b0;
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blank <= 1'b0;
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x <= 0;
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y <= 0;
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end
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always @(posedge clock) begin
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if(clock_en) begin
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hsync <= ~(H_VISIBLE + H_FRONT <= x && x < H_VISIBLE + H_FRONT + H_SYNC);
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vsync <= ~(V_VISIBLE + V_FRONT <= y && y < V_VISIBLE + V_FRONT + V_SYNC);
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blank <= (H_VISIBLE-1 <= x && x < H_VISIBLE-1 + H_FRONT+H_SYNC+H_BACK)
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|| (V_VISIBLE-1 <= y && y < V_VISIBLE-1 + V_FRONT+V_SYNC+V_BACK);
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//blank <= (x >= H_VISIBLE-1 || y >= V_VISIBLE-1);
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if(x >= H_TOTAL-1) begin
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x <= 0;
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y <= (y >= V_TOTAL-1) ? 0 : y + 1;
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end else
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x <= x + 1;
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end
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end
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endmodule
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