21 lines
422 B
Verilog
21 lines
422 B
Verilog
module Clock_divider #(
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parameter CLOCK_RATIO = 100_000_000
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) (
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input clock_in,
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output reg clock_out
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);
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reg [$clog2(CLOCK_RATIO)-1:0] counter;
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initial begin
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clock_out = 1'b0;
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counter = 0;
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end
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always @(posedge clock_in) begin
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clock_out <= (counter >= CLOCK_RATIO-1);
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counter <= (counter >= CLOCK_RATIO-1 ? 0 : counter + 1);
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end
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endmodule
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