55 lines
1.1 KiB
Verilog
55 lines
1.1 KiB
Verilog
`timescale 100ps/10ps
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module testbench ();
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reg clk;
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initial clk = 1'b0;
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always #5 clk = ~clk;
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wire slow_clk;
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wire [1:0] segment_select;
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reg [13:0] counter;
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Clock_divider #(.CLOCK_RATIO(4)) clock_divider (
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.clock_in(clk),
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.clock_out(slow_clk)
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);
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Blinky uut (
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.clock(clk),
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.clock_en(slow_clk)
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);
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Seven_segment_timing seven_segment_timing (
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.clock(clk),
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.sel(segment_select)
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);
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Seven_segment_bcd seven_segment_bcd (
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.clock(clk),
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.value(counter),
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.sel(segment_select)
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);
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VGA_timing vga (
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.clock(clk),
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.clock_en(1'b1)
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);
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always @(posedge clk) begin
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if(slow_clk) counter <= counter + 1;
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end
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initial begin
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$display("Hello, World!");
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$display("Simulation started.");
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$dumpfile("output/testbench.vcd");
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$dumpvars(0, testbench);
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$display("Writing to output/testbench.vcd");
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#5000 $finish();
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end
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endmodule
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