85 lines
1.8 KiB
Verilog
85 lines
1.8 KiB
Verilog
module Basys3_Top (
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input clk,
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output [15:0] led,
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output [6:0] seg,
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output [3:0] an,
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output dp,
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output Hsync,
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output Vsync,
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output [3:0] vgaRed,
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output [3:0] vgaGreen,
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output [3:0] vgaBlue
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);
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assign led[15:1] = 14'b0;
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assign dp = 1'b1;
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wire clk_1Hz;
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wire clk_vga;
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wire clk_sevseg;
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Clock_divider clock_divider_1Hz (
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.clock_in(clk),
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.clock_out(clk_1Hz)
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);
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Clock_divider #(.CLOCK_RATIO(100_000_000/250)) clock_divider_sevseg (
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.clock_in(clk),
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.clock_out(clk_sevseg)
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);
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Clock_divider #(.CLOCK_RATIO(100_000_000/50_000_000)) clock_divider_vga (
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.clock_in(clk),
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.clock_out(clk_vga)
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);
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Blinky blinky (
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.clock(clk),
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.clock_en(clk_1Hz),
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.led(led[0])
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);
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reg [13:0] counter;
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wire [1:0] seven_segment_sel;
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always @(posedge clk) begin
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if(clk_1Hz)
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counter <= counter + 1;
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end
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Seven_segment_timing seven_segment_timing (
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.clock(clk),
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.clock_en(clk_sevseg),
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.sel(seven_segment_sel),
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.an(an)
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);
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Seven_segment_bcd seven_segment_bcd (
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.clock(clk),
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.value(counter),
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.sel(seven_segment_sel),
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.seg(seg)
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);
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wire [9:0] vga_x, vga_y;
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wire vga_blank;
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VGA_timing vga_timing (
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.clock(clk),
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.clock_en(clk_vga),
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.hsync(Hsync),
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.vsync(Vsync),
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.blank(vga_blank),
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.x(vga_x),
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.y(vga_y)
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);
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RAM #(.WIDTH(12), .SIZE(400*300), .INIT_FILENAME("../init/vram.init")) ram (
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.clock(clk),
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.reset(vga_blank),
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.clock_en(clk_vga),
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.addr(400*vga_y[9:1]+vga_x[9:1]),
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.din(12'b0),
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.dout({vgaRed, vgaGreen, vgaBlue})
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);
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endmodule
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