17 lines
223 B
Verilog
17 lines
223 B
Verilog
module Blinky (
|
|
input clock,
|
|
input clock_en,
|
|
output reg led
|
|
);
|
|
|
|
initial begin
|
|
led <= 1'b0;
|
|
end
|
|
|
|
always @(posedge clock) begin
|
|
if(clock_en)
|
|
led <= ~led;
|
|
end
|
|
|
|
endmodule
|