34 lines
786 B
Verilog
34 lines
786 B
Verilog
module RAM #(
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parameter WIDTH = 8,
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parameter SIZE = 128,
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parameter INIT_FILENAME = ""
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) (
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input clock,
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input reset,
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input clock_en,
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input write_en,
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input [$clog2(SIZE)-1:0] addr,
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input [WIDTH-1:0] din,
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output reg [WIDTH-1:0] dout
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);
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reg [WIDTH-1:0] ram[SIZE-1:0], dout;
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integer i;
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initial begin
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if(INIT_FILENAME == "")
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for(i = 0; i < SIZE; i=i+1) ram[i] = 0;
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else
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$readmemb(INIT_FILENAME, ram);
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end
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always @(posedge clock) begin
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if(clock_en) begin
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dout <= reset ? 0 : ram[addr];
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if(write_en)
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ram[addr] <= din;
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end
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end
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endmodule
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