20 lines
342 B
Verilog
20 lines
342 B
Verilog
module Seven_segment_timing (
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input clock,
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input clock_en,
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output reg [1:0] sel,
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output reg [3:0] an
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);
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initial begin
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sel = 0;
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an = 0;
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end
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always @(posedge clock) begin
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an <= ~(4'b0001 << sel);
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if(clock_en)
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sel <= sel + 1;
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end
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endmodule
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