31 lines
1.2 KiB
Tcl
31 lines
1.2 KiB
Tcl
set PROJECT_DIR ..
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set OUTPUT_DIR ./output
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set PART_NO xc7a35tcpg236-1
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file mkdir $OUTPUT_DIR
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read_verilog [ glob $PROJECT_DIR/rtl/*.v ]
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read_xdc $PROJECT_DIR/vivado_flow/Basys3_Master.xdc
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synth_design -top Basys3_Top -part $PART_NO -include_dirs $PROJECT_DIR/rtl
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write_checkpoint -force $OUTPUT_DIR/post_synth.dcp
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report_timing_summary -file $OUTPUT_DIR/post_synth_timing_summary.rpt
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report_power -file $OUTPUT_DIR/post_synth_power.rpt
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opt_design
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place_design
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phys_opt_design
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write_checkpoint -force $OUTPUT_DIR/post_place.dcp
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report_timing_summary -file $OUTPUT_DIR/post_place_timing_summary.rpt
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route_design
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write_checkpoint -force $OUTPUT_DIR/post_route.dcp
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report_timing -sort_by group -max_paths 100 -path_type summary -file $OUTPUT_DIR/post_route_timing.rpt
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report_timing_summary -file $OUTPUT_DIR/post_route_timing_summary.rpt
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report_clock_utilization -file $OUTPUT_DIR/clock_util.rpt
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report_utilization -file $OUTPUT_DIR/post_route_util.rpt
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report_power -file $OUTPUT_DIR/post_route_power.rpt
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report_drc -file $OUTPUT_DIR/post_imp_drc.rpt
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write_bitstream -force $OUTPUT_DIR/$PART_NO.bit
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