first commit

sim/baseball_testbench.sv

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+`timescale 1ns/1ns
+
+module baseball_testbench ();
+	
+	logic clock;
+	logic reset;
+	initial clock = 0;
+	initial reset = 0;
+	always #1 clock = ~clock;
+	
+	logic got_strike;
+	logic got_ball;
+	logic got_foul;
+	logic got_hit;
+	logic got_out;
+	logic [1:0] strike_count;
+	logic [2:0] ball_count;
+	logic [1:0] out_count;
+	logic [3:0] inning_count;
+	logic       team_active;
+	
+	baseball_scoreboard uut(
+		.clock(clock),
+		.reset(reset),
+		.got_strike(got_strike),
+		.got_ball(got_ball),
+		.got_foul(got_foul),
+		.got_hit(got_hit),
+		.got_out(got_out),
+		.strike_count(strike_count),
+		.ball_count(ball_count),
+		.out_count(out_count),
+		.inning_count(inning_count),
+		.team_active(team_active)
+	);
+	
+	initial begin
+		$dumpfile("output/baseball_testbench.vcd");
+		$dumpvars(0, baseball_testbench);
+		
+		got_strike = 0;
+		got_ball = 0;
+		got_foul = 0;
+		got_hit = 0;
+		got_out = 0;
+		
+		@(negedge clock) reset <= '1;
+		@(negedge clock) reset <= '0;
+
+		repeat (9) begin
+			@(negedge clock) got_strike <= '1;
+			@(negedge clock) got_strike <= '0;
+		end
+		
+		repeat (5) begin
+			@(negedge clock) got_foul <= '1;
+			@(negedge clock) got_foul <= '0;
+		end
+		
+		@(negedge clock) got_strike <= '1;
+		@(negedge clock) got_strike <= '0;
+		
+		repeat (2) begin
+			@(negedge clock) got_strike <= '1;
+			@(negedge clock) got_strike <= '0;
+		end
+		
+		repeat (4) begin
+			@(negedge clock) got_ball <= '1;
+			@(negedge clock) got_ball <= '0;
+		end
+		
+		#10 $finish();
+	end
+	
+endmodule

sim/run_iverilog.cmd

@@ -0,0 +1,13 @@
+mkdir output
+
+iverilog -g2012 ^
+	-tvvp ^
+	-I../rtl/ ^
+	-Y.sv ^
+	-y../rtl/common ^
+	-s baseball_testbench ^
+	-ooutput/baseball_testbench.vvp ^
+	baseball_testbench.sv ^
+	../rtl/baseball_scoreboard.sv ^
+	../rtl/baseball_controlpath.sv ^
+	../rtl/baseball_datapath.sv