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Pablo Rodriguez
2025-04-06 00:11:28 -04:00
commit 6206025f5a
16 changed files with 930 additions and 0 deletions
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vivado_flow/run_batch.tcl Normal file
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set PROJECT_DIR ..
set OUTPUT_DIR ./output
set PART_NO xc7a35tcpg236-1
file mkdir $OUTPUT_DIR
read_verilog [ glob $PROJECT_DIR/rtl/*.sv ]
read_verilog [ glob $PROJECT_DIR/rtl/common/*.sv ]
read_xdc $PROJECT_DIR/vivado_flow/Basys3_Master.xdc
synth_design -top basys3_toplevel -part $PART_NO -include_dirs $PROJECT_DIR/rtl
report_timing_summary -file $OUTPUT_DIR/post_synth_timing_summary.rpt
report_power -file $OUTPUT_DIR/post_synth_power.rpt
opt_design
place_design
phys_opt_design
report_timing_summary -file $OUTPUT_DIR/post_place_timing_summary.rpt
route_design
report_timing -sort_by group -max_paths 100 -path_type summary -file $OUTPUT_DIR/post_route_timing.rpt
report_timing_summary -file $OUTPUT_DIR/post_route_timing_summary.rpt
report_clock_utilization -file $OUTPUT_DIR/clock_util.rpt
report_utilization -file $OUTPUT_DIR/post_route_util.rpt
report_power -file $OUTPUT_DIR/post_route_power.rpt
report_drc -file $OUTPUT_DIR/post_imp_drc.rpt
write_bitstream -force $OUTPUT_DIR/$PART_NO.bit