12 lines
288 B
Tcl
12 lines
288 B
Tcl
set PROJECT_DIR ..
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set OUTPUT_DIR ./output
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set PART_NO xc7a35tcpg236-1
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file mkdir $OUTPUT_DIR
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read_verilog [ glob $PROJECT_DIR/rtl/*.v ]
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read_xdc $PROJECT_DIR/vivado_flow/Basys3_Master.xdc
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synth_design -top Basys3_Top -rtl -include_dirs $PROJECT_DIR/rtl
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start_gui
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