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README.TXT

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+Video Card
+	- PR 2025
+
+Project to practice Verilog and FPGA design flow in Vivado.
+
+The design will display a static image to a monitor via the VGA
+port of the Basys3 board. For demonstration purposes an LED light
+and the seven segment display also light up. The image is stored
+in the FPGA's block RAM, it can be customized by using the Python
+script provided in the tools directory to convert any image file
+you want to display:
+	python3 tools/main.py input.png > init/vram.init
+
+To simulate; go into the `sim` directory and run `make`;
+then use `vvp output/testbench.vvp` to create the waveform dump.
+
+To synthesize the design for the Basys3 board; enter the `vivado_flow` directory
+and run `vivado -mode batch -source run_batch.tcl`. This will create the bitstream
+file to program the FPGA.
+
+Basys3 resources:
+
+  Diligent reference manual:
+  https://digilent.com/reference/programmable-logic/basys-3/reference-manual
+
+Xilinx Vivado resources:
+
+  Block RAM and HDL coding techniques:
+  https://docs.amd.com/r/en-US/ug901-vivado-synthesis/Single-Port-Block-RAM-with-Resettable-Data-Output-Verilog
+
+  Design flow with Tcl scripts:
+  https://docs.amd.com/r/en-US/ug894-vivado-tcl-scripting/Compilation-with-a-Non-Project-Flow