first commit

rtl/Basys3_Top.v

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+module Basys3_Top (
+    input         clk,
+    output [15:0] led,
+    output  [6:0] seg,
+    output  [3:0] an,
+    output        dp,
+    output        Hsync,
+    output        Vsync,
+    output  [3:0] vgaRed,
+    output  [3:0] vgaGreen,
+    output  [3:0] vgaBlue
+);
+    assign led[15:1] = 14'b0;
+    assign dp = 1'b1;
+
+    wire clk_1Hz;
+    wire clk_vga;
+    wire clk_sevseg;
+    
+    Clock_divider clock_divider_1Hz (
+        .clock_in(clk),
+        .clock_out(clk_1Hz)
+    );
+    
+    Clock_divider #(.CLOCK_RATIO(100_000_000/250)) clock_divider_sevseg (
+        .clock_in(clk),
+        .clock_out(clk_sevseg)
+    );
+    
+    Clock_divider #(.CLOCK_RATIO(100_000_000/50_000_000)) clock_divider_vga (
+        .clock_in(clk),
+        .clock_out(clk_vga)
+    );
+    
+    Blinky blinky (
+        .clock(clk),
+        .clock_en(clk_1Hz),
+        .led(led[0])
+    );
+    
+    reg [13:0] counter;
+    wire [1:0] seven_segment_sel;
+    
+    always @(posedge clk) begin
+        if(clk_1Hz)
+            counter <= counter + 1;
+    end
+    
+    Seven_segment_timing seven_segment_timing (
+        .clock(clk),
+        .clock_en(clk_sevseg),
+        .sel(seven_segment_sel),
+        .an(an)
+    );
+    
+    Seven_segment_bcd seven_segment_bcd (
+        .clock(clk),
+        .value(counter),
+        .sel(seven_segment_sel),
+        .seg(seg)
+    );
+    
+    wire [9:0] vga_x, vga_y;
+    wire vga_blank;
+    VGA_timing vga_timing (
+        .clock(clk),
+        .clock_en(clk_vga),
+        .hsync(Hsync),
+        .vsync(Vsync),
+        .blank(vga_blank),
+        .x(vga_x),
+        .y(vga_y)
+    );
+    
+    RAM #(.WIDTH(12), .SIZE(400*300), .INIT_FILENAME("../init/vram.init")) ram (
+        .clock(clk),
+        .reset(vga_blank),
+        .clock_en(clk_vga),
+        .addr(400*vga_y[9:1]+vga_x[9:1]),
+        .din(12'b0),
+        .dout({vgaRed, vgaGreen, vgaBlue})
+    );
+
+endmodule