first commit

rtl/Blinky.v

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+module Blinky (
+    input clock,
+    input clock_en,
+    output reg led
+);
+
+    initial begin
+        led <= 1'b0;
+    end
+
+    always @(posedge clock) begin
+        if(clock_en)
+            led <= ~led;
+    end
+
+endmodule