first commit

sim/Makefile

@@ -0,0 +1,10 @@
+SOURCES = ../rtl/Blinky.v \
+	../rtl/Clock_divider.v \
+	../rtl/Bin2bcd.v \
+	../rtl/Seven_segment_bcd.v \
+	../rtl/Seven_segment_timing.v \
+	../rtl/VGA_timing.v
+
+output/testbench.vvp: testbench.v $(SOURCES)
+	mkdir -p output
+	iverilog -Wall -tvvp -I../rtl -stestbench -o $@ $< $(SOURCES)