prodriguez/fpga_video_card
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Pablo Rodriguez
2025-11-24 21:44:39 -05:00
commit 1b017953ee
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vivado_flow/run_elaborate.tcl Normal file
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set PROJECT_DIR ..
set OUTPUT_DIR ./output
set PART_NO xc7a35tcpg236-1
file mkdir $OUTPUT_DIR
read_verilog [ glob $PROJECT_DIR/rtl/*.v ]
read_xdc $PROJECT_DIR/vivado_flow/Basys3_Master.xdc
synth_design -top Basys3_Top -rtl -include_dirs $PROJECT_DIR/rtl
start_gui