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rtl/VGA_timing.v

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+module VGA_timing #(
+    // VESA 800x600@72 use with 50MHz pixel clock
+    parameter H_VISIBLE = 800,  // Visible area
+    parameter H_FRONT   = 56,   // Front porch
+    parameter H_SYNC    = 120,  // Sync pulse
+    parameter H_BACK    = 64,   // Back porch
+    parameter H_TOTAL   = 1040, // Whole line
+    
+    parameter V_VISIBLE = 600, // Visible area
+    parameter V_FRONT   = 37,  // Front porch
+    parameter V_SYNC    = 6,   // Sync pulse
+    parameter V_BACK    = 23,  // Back porch
+    parameter V_TOTAL   = 666  // Whole line
+) (
+    input                            clock,
+    input                            clock_en,
+    output reg                       hsync,
+    output reg                       vsync,
+    output reg                       blank,
+    output reg [$clog2(H_TOTAL)-1:0] x,
+    output reg [$clog2(V_TOTAL)-1:0] y
+);
+    
+    initial begin
+        hsync <= 1'b0;
+        vsync <= 1'b0;
+        blank <= 1'b0;
+        x <= 0;
+        y <= 0;
+    end
+    
+    always @(posedge clock) begin
+        if(clock_en) begin
+            hsync <= ~(H_VISIBLE + H_FRONT <= x && x < H_VISIBLE + H_FRONT + H_SYNC);
+            vsync <= ~(V_VISIBLE + V_FRONT <= y && y < V_VISIBLE + V_FRONT + V_SYNC);
+            blank <= (H_VISIBLE-1 <= x && x < H_VISIBLE-1 + H_FRONT+H_SYNC+H_BACK)
+                  || (V_VISIBLE-1 <= y && y < V_VISIBLE-1 + V_FRONT+V_SYNC+V_BACK);
+            //blank <= (x >= H_VISIBLE-1 || y >= V_VISIBLE-1);
+            if(x >= H_TOTAL-1) begin
+                x <= 0;
+                y <= (y >= V_TOTAL-1) ? 0 : y + 1;
+            end else
+                x <= x + 1;
+        end
+    end
+
+endmodule