first commit

rtl/common/multiplexer.sv

@@ -0,0 +1,19 @@
+module multiplexer #(
+	parameter WIDTH = 32,
+	parameter CHANNELS = 2
+) (
+	input  logic [$clog2(CHANNELS)-1:0] sel,
+	input  logic [(CHANNELS*WIDTH)-1:0] in_bus,
+	output logic            [WIDTH-1:0] out
+);
+
+	genvar ig;
+	
+	logic [WIDTH-1:0] in_array [CHANNELS];
+	assign out = in_array[sel];
+	
+	for(ig = 0; ig < CHANNELS; ig = ig + 1) begin
+		assign in_array[(CHANNELS - 1) - ig] = in_bus[ig * WIDTH +: WIDTH];
+	end
+
+endmodule

rtl/common/multiplexer2.sv

@@ -0,0 +1,16 @@
+module multiplexer2 #(
+	parameter WIDTH = 32
+) (
+	input  logic             sel,
+	input  logic [WIDTH-1:0] in0,
+	input  logic [WIDTH-1:0] in1,
+	output logic [WIDTH-1:0] out
+);
+
+	multiplexer #(.WIDTH(WIDTH), .CHANNELS(2)) multiplexer_inst (
+		.sel(sel),
+		.in_bus({in0, in1}),
+		.out(out)
+	);
+	
+endmodule

rtl/common/multiplexer4.sv

@@ -0,0 +1,18 @@
+module multiplexer4 #(
+	parameter WIDTH = 32
+) (
+	input  logic       [1:0] sel,
+	input  logic [WIDTH-1:0] in0,
+	input  logic [WIDTH-1:0] in1,
+	input  logic [WIDTH-1:0] in2,
+	input  logic [WIDTH-1:0] in3,
+	output logic [WIDTH-1:0] out
+);
+
+	multiplexer #(.WIDTH(WIDTH), .CHANNELS(4)) multiplexer_inst (
+		.sel(sel),
+		.in_bus({in0, in1, in2, in3}),
+		.out(out)
+	);
+	
+endmodule

rtl/common/register.sv

@@ -0,0 +1,18 @@
+module register #(
+	parameter WIDTH = 32,
+	parameter RESET = 0
+) (
+	input  logic             clock,
+	input  logic             reset,
+	input  logic             write_en,
+	input  logic [WIDTH-1:0] next,
+	output logic [WIDTH-1:0] value
+);
+
+	always_ff @(posedge clock, posedge reset)
+		if(reset)
+			value <= RESET;
+		else if(write_en)
+			value <= next;
+
+endmodule